1. Field of the Invention
The invention relates generally to digital logic systems and more particularly to high speed digital logic systems.
2. Description of the Related Art
There is a trend in present digital systems toward increased data processing speeds. This trend has spurred the development of very high speed integrated circuits. For example, Rory L. Von Tuyl, et al in "GaAs MESFET Logic with 4-GHz Clock Rate", I.E.E.E. Journal of Solid State Circuits, Vol. SC-12, No. 5, October 1977, described high-speed, GaAs MESFET integrated circuit buffered field-effect-transistor (FET) gates capable of implementing NAND-AND and NOR-OR type logic. The high-speed capabilities of such merged logic gate structures is largely due to the fact that there is substantially only one logic gate propagation delay between the application of an input data signal to such a gate and the provision of an output signal by the gate. The development of such high speed gates has made possible a contemporaneous development of digital logic systems which operate at frequencies high enough to take maximum advantage of their high speed.
The flip-flop and its constituent, the latch cell, are key building blocks in digital logic systems, and therefore, there has been a growing need for very high-speed flip-flops and latch cells. Von Tuyl, et al described a high-speed master-slave set-reset (SR) flip-flop utilizing complementary clocks and incorporating logic gates of the type described above. An exemplary flip-flop of the type disclosed by Von Tuyl, et al is illustrated in FIG. 1.
The high-speed characteristics of the flip-flop described by Von Tuyl, et al largely stemmed from the fact that a data storage slave latch was active only during the portion of the clocking cycle when the data storage command (CLOCK) was activated, and a data entry master latch was active only during the portion of the clocking cycle when the data entry command (CLOCK) was activated. Thus, the flip-flop took advantage of the high-speed characteristics of its constituent logic gates, and for example, the time necessary for data entry into the data entry master latch was substantially only one logic gate propagation delay (e.g., from R to Q.sub.m).
While high-speed flip-flops of the type described by Von Tuyl, et al generally have been satisfactory, there have been limitations with their use. For example, flip-flops of the type described by Von Tuyl, et al have been implemented as high-speed D flip-flops by inputting data corresponding to a D signal into a terminal corresponding to the S input and by inputting data corresponding to a D signal into a terminal corresponding to the R input. In complex logic systems, however, often it is desirable to have a D flip-flop capable of receiving multiple D data input signals; that is, instead of providing one data input signal to a single S terminal, often it is desirable to provide a plurality of data input signals to a plurality of S terminals. Unfortunately, the flip-flop disclosed by Von Tuyl, et al does not satisfactorily implement a D flip-flop which can receive multiple data input signals. This is because the provision of multiple data input signals to multiple S terminals of a master latch would require the provision of corresponding multiple complementary input signals to multiple R terminals of the master latch. A master latch of the type disclosed by Von Tuyl, et al, however, does not satisfactorily process multiple input signals and their corresponding multiple complementary signals.
One solution to this problem might be to add a differential stage or an additional inverting stage to a master latch to internally generate a single D input and a corresponding single D input from multiple data input signals. For example, Zuleeg, et al in U.S. Pat. No. 4,038,563 discloses a source-coupled logic NOR/NAND gate comprising an inverter for receiving three input signals and providing two complementary output signals. A disadvantage of such a solution is that a differential stage or an inverting stage would require additional propagation delay which could slow the operation of the flip-flop to such an extent that it would not take full advantage of the high-speed of its constituent logic gates. Therefore, such solutions significantly degrade the high-speed performance of the flip-flop and substantially diminish its usefulness in high-speed systems.
Thus, there has been a need for a high-speed electronic circuit capable of receiving multiple data input signals and generating complementary output signals with substantially only one logic gate delay between the input signals and the corresponding output signals. The present invention meets this need.